The present invention relates to a vector processing unit.
For computing a large-sized matrix which frequently appears in the scientic calculation, a vector processing unit having a plurality of vector registers and a plurality of arithmetic and logic units (ALU's) was disclosed, for example, in a literature of Richard M. Russel, "The Cray-1 Computer System" in Communications of the ACM, January 1978, Vol. 21, No. 1, p.p. 63-72. In such a vector processing unit, the data stored in a vector register can be read out with one vector instruction while data is being written into the vector register with another vector instruction, and in such case, these two vector instructions are referred to as being chained.
In such a vector processing unit, one of the factors determining the vector processing time is the number of chains attained. The number of chains depends upon the conflict situation occurring between vector registers, between ALU's, and between memory requesters. An example of such a vector processing unit will now be described. In this example, the ALU has one adder, one multiplier and three memory requesters. Hereafter, the vector register is referred to as a VR and the ALU and the memory requester are referred to simply as resources.